Among many semiconductor packages, BGA (Ball Grid Array) packages implement PCB substrates as chip carriers. Since the circuitry of a substrate can be isolated in different metal layers electrically connected with plated through holes (PTHs), therefore, redistributing pin assignments can easily be done by multiple circuit layers of a substrate and PTHs. Chip-On-Lead (COL) packages are another well-known packages implementing leadframes as chip carriers where the back surface of a chip is attached to a plurality of leads of a leadframe. Even though COL package has the advantages of lower cost, however, the wire-bonding area is limited and it is very hard to redistribute pin assignments. Moreover, there is only one layer of leads of a leadframe which is mostly covered by a chip and the leads of a leadframe have to be clamped by top and bottom mold tools during molding processes. It is very difficult for COL packages to have multi-layer, electrically-isolated metal circuitry as a substrate to redistribute pin assignments. A COL leadframe-based semiconductor package related patent has been disclosed in Taiwan Patent No. 1287876, entitled “Semiconductor package”.
A cross-sectional view of a conventional COL leadframe-based semiconductor package 100 is shown in FIG. 1. A partial top view of a leadframe segment 120 inside the encapsulant of the conventional leadframe-based semiconductor package 100 is shown in FIG. 2. A partial top view of some components of the conventional leadframe-based semiconductor package 100 inside an encapsulant 110 is shown in FIG. 3.
The conventional semiconductor package 100 primarily comprises an encapsulant 110, a leadframe segment 120, a plurality of chips 130 and 170 and a plurality of first bonding wires 141 and second bonding wires 142. As shown in FIG. 2, the leadframe segment 120 includes a plurality of leads 121 and a plurality of short leads 126. The chips 130 and 170 are carried on the leads 121. Each lead 121 has an internal portion 124 inside the encapsulant 110 and an external portion 125 extended outside the encapsulant 110. The back surface of the first chip 130 is attached to the internal portions 124 of the leads 121 by adhesive tapes, therefore, the sections of the internal portions 124 covered by the chip 130 can not be used for wire bonding. As shown in FIG. 1 and FIG. 3, normally the first bonding wires 141 electrically connect a plurality of first electrodes 131 on the active surface of the first chip 130 to the internal ends of the internal portions 124 not covered by the chip 130 and to the internal ends of the short leads 126. The second chip 170 is stacked on the first chip 130, as shown in FIG. 1 and FIG. 3, where the second bonding wires 142 electrically connect a plurality of second electrodes 171 on the second chip 170 to the internal ends of the internal portions 124 not covered by the first chip 130 and to the internal ends of the short leads 126. Therefore, the wire-bonding area of the chips in a COL package is very limited and complicated, especially for multi-chip stacking packages where the wire-bonding density is much higher. Parts of the wire bonding diagram of the first bonding wires 141 and the second bonding wires 142 is shown in FIG. 3 if the first bonding wires 141 and the second bonding wires 142 can not cross bonding, then the pin assignment can not be redistributed. If the first bonding wires 141 and the second bonding wires 142 are cross bonding due to pin assignments, then the gaps between the crossing bonding wires will be smaller leading to electrical short caused by wire sweeping during molding.
A leadframe-based but not COL type semiconductor package with redistribution of pin assignments is disclosed in U.S. Pat. No. 5,206,536, where the semiconductor package is a Lead-On-Chip (LOC) package and the fingers of the leads are attached to the tape disposed on the active surface of a chip. Further attached to the tape is a comb-like conductive layer as electrical redistributing components. The comb-like conductive layer has a plurality of comb teeth between the lead fingers to redistribute pin assignments. Additionally, the leads have a plurality of downset bends adjacent to the lead fingers to avoid electrical short with the comb-like conductive layer. Since the locations of the lead fingers and the comb-like conductive layer on the active surface of a chip is necessary to implement this technology, it can not be implemented in Chip-On-Lead (COL) packages nor multi-chip packages.